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Control IC for Switched-Mode Power Supplies using MOS-Transistors
TDA 4605
Bipolar IC
Features
q Fold-back characteristic provides overload protection for q q q q q q q
external components Burst operation under short-circuit conditions Loop error protection Switch-off if line voltage is too low (undervoltage switch-off) Line voltage compensation of overload point Soft-start for quiet start-up Chip-over temperature protection (thermal shutdown) On-chip parasitic transformer oscillation suppression circuitry
P-DIP-8-1
Type TDA 4605
Ordering Code Q67000-A8078
Package P-DIP-8-1
The IC TDA 4605-1 controls the MOS-power transistor and performs all necessary regulation and monitoring functions in free running flyback converters. Since good load regulation over a wide load range is attained, this IC is applicable tor consumer and industrial power supplies. The serial circuit of power transistor and primary winding of the flyback transformer is connected to the input voltage. During the switch - on period of the transistor, energy is stored in the transformer and during the switch - off period it is fed to the load via the secondary winding. By varying switchon time of the power transistor, the IC controls each portion of energy transferred to the secondary side such that the output voltage remains nearly independent ot load variations. The required control information is taken from the input voltage during the switch-on period and from a regulation winding during the switch-off period.
Semiconductor Group
33
06.94
TDA 4605
In the different load ranges the switched-mode power supply (SMPS) behaves as follow: No load operation: The power supply unit oscillates at its resonant frequency typ. 100 kHz to 200 kHz. Depending upon the transformator windings the output voltage can be slightly above nominal value. Nominal operation: The switching frequency declines with increasing load and decreasing AC-voltage. The duty factor primarly depends on the AC-voltage. The output voltage is load-dependent only. Overload point: Maximal output power is available at this point ot the output characteristic. Overload: The energy transferred per operation cycle is limited at the top. Therefore the output voltage declines by secondary overloading.
Semiconductor Group
34
TDA 4605
Pin Definitions and Functions Pin No. 1 Function Regulating Voltage: Information input concerning secondary voltage. By comparing the regulating voltage - obtained from the regulating winding ot the transformer - with the internal reference voltage, the output impulse width on pin 5 is adapted to the load ot the secondary side (normal, overload, short-circuit, no load). Primary Current Simulation: Information input regarding the primary current. The primary current rise in the primary winding is simulated at pin 2 as a voltage rise by means ot external RC-element. When a value is reached that is derived from the regulating voltage at pin 1, the output impulse at pin 5 is terminated. The RC-element serves to set the maximum power at the overload point set. Input for Primary Voltage Monitoring: In the normal operation V3 is moving between the thresholds V3H and V3L (V3H > V3 > V3L). V3 < V3L: SMPS is switched OFF (line voltage too low). V3 > V3H : Compensation of the overload point regulation (controlled by pin 2) starts at V3H : V3L = 1.7. Ground Output: Push-pull-output provides 1 A for rapid charge and discharge of the gate capacitance ot the power MOS-transistor. Supply Voltage Input: A stable internal reference voltage VREF is derived from the supply voltage also the switching thresholds V6A , V6E , V6 max and V6 min for the supply voltage detector. If V6 > V6E then VREF is switched on and swiched off when V6 < V6A . In addition the logic is only enable for V6 min < V6 < V6 max. Soft-Start: Input for soft-start. Start-up will begin with short pulses by connecting a capacitor from pin 7 to ground. Zero Detector: Input tor the oscillation feedback. After starting oscillation, every zero transit of the feedback voltage (falling edge) triggers an output impulse at pin 5. The trigger threshold is at + 50 mV typical.
2
3
4 5 6
7 8
Semiconductor Group
35
TDA 4605
Block Diagram Semiconductor Group 36
TDA 4605
Circuit Description Application Circuit Application circuit shows a flyback converter for video recorders with a power rating of 50 W. The circuit is designed as a wide-range power supply tor AC-line voltages ot 90 to 270 V. The AC-input voltage is rectified by bridge rectifier GR1 and smoothed by C1 . The NTC limits the rush in current. In the period before the switch-on threshold is reached the IC is supplied via resistor R 1 ; during the start-up phase it uses the energy stored in C2 , under steady-state conditions the IC receives its supply voltage from transformer winding n1 via diode D1. The switching transistor T1 is a BUZ 90. The parallel-connected capacitor C3 and the inductance ot primary winding 112 determine the system resonance frequency. The R 2 - C4 - D2 circuitry limits overshoot peaks, and R 3 protects the gate of T1 against static charges. While T1 conducts, the current rise in the primary winding depends on the winding's inductance and the VC1 voltage. A voltage reproduction ot the current rise is tabbed using the R4 - C5 network and forwarded into pin 2 ot the IC. The RC-time constant ot R 4 , R 5 must be dimensioned correctly in order to prevent driving the transformer core into saturation. The R 10/R 11 divider ratio provides the line voltage threshold controlling the undervoltage control circuit in the IC. The voltage present at pin 3 also determines the overload. Detection of overload together with the current characteristic at pin 2 controls the on period ot T1. This keeps the cut-off point stable even with higher AC-line voltages. Regulation of the switched-mode power supply is via pin 1. The control voltage of winding n1 during the off-period of T1 is rectified by D3, smoothed by C6 and stepped down at an adjustable ratio by R 5 , R 6 and R 7 . The R 6 - C7 network suppresses parasitic overshoots (transformer oscillation). The peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage applied across the control winding, and hence the output voltages, are at the desired level. When the transformer has supplied its energy to the load, the control voltage passes through zero. The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero crossings are also produced by transformer oscillation after T1 has turned off if output is short-circuited. Therefore the IC ignores zero crossings occurring within a specitied period of time after T1 turn-off. The capacitor C8 connected to pin 7 causes the power supply to be started with shorter pulses to keep the operating ftrequency outside the audible range during start-up. On the secondary side, tive output voltages are produced across winding n3 to n7 rectified by D4 to D8 and smoothed by C9 to C13 . Resistors R 12 , R 14 and R 19 to R 21 are used as bleeder resistors. Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output circuits, which are designed to supply only small loads.
Semiconductor Group
37
TDA 4605
Block Diagram Pin 1 The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR in the regulating and overload amplifier. The output of this stage is ted to the stop comparator. Pin 2 A voltage proportional to the drain current ot the switching transistor is generated there by the external RC-combination in conjunction with the primary current transducer. The output of this transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage V2 exceeds the output voltage of the regulating amplifier, the logic is reset by the stop comparator and consequently the output ot pin 5 is switched to low potential. Further inputs tor the logic stage are the output for the start impulse generator with the stable reference potential VST and the supply voltage monitor. Pin 3 The down-divide primary voltage applied there stabilizes the overload point. In addition the logic is disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary voltage monitor block. Pin 4 Ground Pin 5 In the output stage the output signals produced by the logic are shifted to a leved suitable for MOSpower transistors. Pin 6 From the supply voltage V6 are derived a stable internal reference VREF and the switching threshold V6A , V6E , V6 max and V6 min for the supply voltage monitor. All reference values (VR , V2B , VST) are derived from VREF . If V6 > VVE the VREF is switched on and switched off when V6 < V6A . In addition, the logic is released only for V6 min < V6 < V6 max . Pin 7 The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is connected to ground by a capacitor.
Semiconductor Group
38
TDA 4605
Pin 8 The zero detector controlling the logic block recognizes the transformer being discharged by positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new pulse (double-pulsing), because an internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse. Start-Up Behaviour The start-up behaviour of the application circuit per sheet 48 is represented on sheet 50 for a line voltage barely above the lower acceptable limit voltage value (without soft-start). After applying the line voltage at the time t0 to the tollowing voltages built up: - V6 corresponding to the half-wave charge current over R 1 - V2 to V2 max (typically 6.6 V) - V3 to the value determined by the divider R 10/R 11 . The current drawn by the IC in this case is less than 1.6 mA. If V6 reaches the threshold V6E (time point t1), the IC switches on the internal reference voltage. The currentdraw max. rises to 12 mA. The primary current- voltage reproducer regulates V2 down to V2E and the starting impulse generator generates the starting impulses from time point t5 to t6 . The feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are controlled in width by regulating voltage of pin 1. When switching on this corresponds to a short-circuit event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width depending on the regulating voltage feedback (the IC operates in the overload range). The maximum pulse width is reached at time point t2 (V2 = V2 max). The IC operates at the overload point. Thereafter the peak values ot V2 decrease rapidly, as the IC is operating within the regulation range. The regulating loop has built up. If voltage V6 falls below the switch-off threshold V6 min before the reversal point is reached, the starting attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V6 further decreases to V6 . The IC switches off; V6 can rise again (time point 14) and a new start-up attempt begins at time point t1 . If the rectified alternating line voltage (primary voltage) collapses during load, V3 can fall below V3A , as is happening at time point t3 (switch-on attempt when voltage is too low). The primary voltage monitor then clamps V3 to V3S until the IC switches off (V6 < V6A). Then a new start-up attempt begins at time point t1 .
Semiconductor Group
39
TDA 4605
Regulation, Overload and No-Load Behaviour When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is 400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V5 = H). The peak voltage value at pin 2 increases up to V2S max . If the secondary load is further increased, the overload amplifier begins to regulate the pulse width downward. This point is referred to as the overload point of the power supply. As the IC supply voltage V6 is directly proportional to the secondary voltage, it goes down in accordance with the overload regulation behaviour. If V6 falls below the value V6 min , the IC goes into burst operation. As the time constant of the half-wave charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back to the pulse width tpk . This pulse width must remain possible, in order to permit the IC to start-up without problems from the virtual short circuit, which every switching on with V1 = 0 represents. If the secondary side is unloaded, the loading impulses (V5 = H) become shorter. The frequency increases up to the resonance frequency of the system. If the load is further reduced, the secondary voltages and V6 increase. When V6 = V6 max , the logic is blocked. The IC converts to burst operation. This renders the circuit absolutely safe under no-load conditions. Behaviour when Temperature Exceeds Limit An integrated temperature protection disables the logic when the chip temperature becomes too high. The IC automatically interrogates the temperature and starts as soon as the temperature decreases to permissible values.
Semiconductor Group
40
TDA 4605
Absolute Maximum Ratings TA = 25 C Parameter Voltages pin 1 pin 2 pin 3 pin 5 pin 6 pin 7 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 Symbol Limit Values min. max. 3 V V V V V V mA mA mA A A A mA mA C C - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 Unit Remarks
V1 V2 V3 V5 V6 V7 V1 V2 V3 V4 V5 V6 V7 V8 Tj Tstg
V6
20 6 3 3 3
Supply voltage
Currents
- 1.5 - 1.5
-3 - 40
1.5 1.5 3 3 125 125
t p 50 s; v 0.1*) t p 50 s; v 0.1 t p 50 s; v 0.1
Junction temperature Storage temperature Operating Range Supply voltage Ambient temperature Heat resistance Junction environment Junction case
*)
V6 TA R th JE R th JC
8 - 20
14 85 100 70
V C K/W K/W
IC "on"
measured at pin 4
t p= pulse width
v= duty circle
Semiconductor Group
41
TDA 4605
Characteristics TA = 25 C Parameter Symbol Limit Values min. Start-Up Hysteresis Start-up current Switch-on voltage Switch-off voltage Switch-on current Switch-off current typ. max. Unit Test Condition Test Circuit
I 6E0 V6E V6A I 6E1 I 6A1
0.5 11 6.4 7 6.5
1.1 12 6.9 9 8
1.6 13 7.4 12 10
mA V V mA mA
V6 = V6E
1 1 1
V6 = V6E V6 = V6A
1 1
Voltage Clamp (V6 = 10 V, IC switched off) At pin 2 (V6 V6E) At pin 3 (V6 V6E) Regulation Range Regulation input voltage Voltage gain regulation range Regulation transmittance
V2 max V3 max
5.6 5.6
6.6 6.6
7.6 7.6
V V
I 2 = 1 mA I 3 = 1 mA
1 1
V1R
370
400
430
mV
2
- VR
47
50 20
53
dB k
VR = d (V2S - V2B)/- dV1 RR = d (V2S - V2B)/- dI1
2 2
RR
Primary Current Reproducer Basic value Input resistance R2B = V2B/I2B Slew rate falling edge
V2B R 2B
0.90
1.00 25
1.15 40
V
2
V3 = 1.5 V; 2 1.2 V < V2 < 3 V 0.1 mA < I 2B < 3 mA
2
dV2/dt
-1
V
Semiconductor Group
42
TDA 4605
Characteristics (cont'd) TA = 25 C Parameter Symbol Limit Values min. typ. max. Unit Test Condition Test Circuit
Overload Range and Short-Circuit Operation Overload range lower V1U limit Voltage gain in overload range Input current in short circuit operation Peak value in overload range Peak value in short circuit operation 60 1 90 230 2 120 3.0 2.2 2.6 3.0 290 3 180 A V V mV 2
VU
- I1
VU = d
(V2S - V2B)/dV1
2 2 2 2
V1 = 0 V V1 = V1R - 10 mV V1 = 0 V
V2U V2K
Generally Valid Data (V6 = 10 V) Overload Point Correction Overload point correction current - I2 400 660 850 A
V3'= 4 V; V2'= 0 V
1
Zero Transition Detector Voltage Positive clamp Negative clamp Threshold value Input current Delay time between V8 and V5 Zero detector disable time
V8P V8N V8S
- I8
0.70 40 0.2 2
0.75 50 2 0.4 2
0.80
V mV
I8 = 1 mA I8 = - 1 mA V8 = 0
2 2 2 2 2
- 0.15 - 0.22 - 0.25 V 4 0.7 6 A s s
td2 tUL
Semiconductor Group
43
TDA 4605
Characteristics (cont'd) TA = 25 C Parameter Symbol Limit Values min. Output Stage Saturation voltages S in position 1 Output sourcing Output sourcing Output sinking Output sinking Output slew rate Rising slope Falling slope Soft-Start Open-circuit Input resistance Peak voltage Protection Circuit Undervoltage protection for V6 at pin 5 = V5 min if V6 < V6 min (definition: V6 min = V6A + V6) Overvoltage protection for V6 voltage at pin 5 = V5 min if V6 > V6 max Undervoltage protection for VAC voltage at pin 5 = V5 min if V3 < V3A Over temperature chip temperature for V6 100 mV 2 typ. max. Unit Test Condition Test Circuit
VSat0 VSat0 VSatV VSatV
+ dV5/dt + dV5/dt
1.5 2.5 1.0 1.4 50 80
2.0 3.0 1.2 1.8
V V V V V/s V/s
I 5 = - 0.1 A I5=-1A I 5 = 0.1 A I 5 = 0.5 A
1 1 1 1 2 2
V7 R 7L V2S
2.2 4 1.0
2.6 6 1.2
2.9 9 1.4
V k V
V1 = 0
0.5 V V7 3 V
2 2 2
V7 = 0
V6 max
14
15
16
V
2
V3A
925
1000
1075
mV
V2' = 0 V
1
V5 min
Tj
125
C
-
2
Semiconductor Group
44
TDA 4605
Characteristics (cont'd) TA = 25 C Parameter Symbol Limit Values min. Voltage at pin 3 when protection function occurred; (V3 will be clamped until V6 < V6A) V3S Burst operation quiescient current typ. max. Unit Test Condition Test Circuit
0.4 8
0.8
V mA
I 3 = 1 mA V3 = V2 = 0 V
1 1
I6
Semiconductor Group
45
TDA 4605
TDA 4605
Test Circuit 1
TDA 4605
Test Circuit 2
Semiconductor Group
46
TDA 4605
Application Circuit Semiconductor Group 47
TDA 4605
Diagrams
Semiconductor Group
48
TDA 4605
Semiconductor Group
49
TDA 4605
Start-Up Hysteresis
Semiconductor Group
50
TDA 4605
Operation in Test Circuit 2 Semiconductor Group 51
TDA 4605
Start-Up Current as a Function of the Ambient Temperature
Overload Point Correction as a Function of the Voltage at Pin 3
Peak Value of the Primary Current Reproduction Voltage as a Function of the Regulating Voltage
Peak Value of the Primary Current Reproduction Voltage by Loading Pin 7
Semiconductor Group
52
TDA 4605
Recommended Heat Sink by 60 C Ambient Temperature Narrow Range 180 V ... 270 V ~
Narrow Range 180 V ... 270 V ~
Semiconductor Group
53

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